module Shifter (value_in, shiftop, shiftamt, result);

    // Input
	input signed [31:0]     value_in;
	input         [1:0]     shiftop;
	input         [4:0]     shiftamt;

	// Output
	output signed [31:0] result;

    // Wire assignment
    reg signed [31:0] result_reg;
    assign result = result_reg;

    // Temporary register
    reg [6:0] i;

    always @(value_in or shiftop or shiftamt) begin

        // Shift operations
        case (shiftop)
    
            2'b00: begin
                // Shift right logic
                result_reg = (value_in >> shiftamt);
            end
    
            2'b01: begin
    
                // Shift right arithmetic
                for (i = 0; i < 32; i = i + 1) begin
                    
                    if ((i + shiftamt) < 32) begin
                        result_reg[i] = value_in[(i + shiftamt)];
                    end else begin
                        result_reg[i] = value_in[31];
                    end

                end
                
            end
        
            2'b10: begin
                // Shift left logic
                result_reg = value_in << shiftamt;
            end
    
            default: begin
                result_reg = 32'bz;
            end
    
        endcase
    end

endmodule
